Lavoro Builder Roma
Junior FPGA Designer
ELT Group - Formello, Lazio, it (+1 località)
, Static Timing Analysis Knowledge of Model Based design methodologies (Matlab Simulink, System Generator, DSP Builder, HDL Coder) Knowledge of Intel and Xilinx FPGA Architectures, design Suites (Vivado
da: it.talent.com - 9 giorni fa